DFI UT P35-T2R: Tweakers Rejoice!
by Rajinder Gill on October 18, 2007 2:00 PM EST- Posted in
- Motherboards
BIOS TRD Phase Adjust
465FSB BIOS Settings
For our 465 FSB Prime stable test, we used the 333/800 strap. We set Performance Level 7, targeted a 465FSB x 8 CPU speed, and ran 4GB of OCZ Flex 9200. The remaining BIOS DRAM Settings were as follows:
Even though we have set Performance Level 7 in the DRAM page, this particular TRD Phase sequence is virtually running a Performance Level of 6 throughout the entire TRD cycle with the exception of a single TRD phase set to 7 (Channel 2 Phase 1) to create the breathing space necessary for the Northbridge to hold steady at 465FSB with 4GB of RAM. When setting a series of phases to ENABLED on both channels, Channel 2 will require an offset as can be seen in the list of settings we used above. If Channel 1 Phase 0, Phase 1 and Channel 2 Phase 0 are set to ENABLED, Channel 2 Phase 1 must be set to AUTO.
Running two or more corresponding phases at ENABLED on both channels is more aggressive, as it sets the corresponding TRD phase registers to -1 at the same point of the TRD cycle, resulting in a lower latency and thus a higher load on the chipset. The general advantage of TRD phase adjustments is to increase FSB margins while retaining significant amounts of latency and bandwidth at FSBs that fall between the borders of two Performance Levels.
Setting a single channel's phase to ENABLED while the corresponding phase for the other channel is set to AUTO results in a very slight gain in latency and bandwidth, which can be useful for maximizing overall performance.
The above timing and phase combinations are only applicable for the setting of 465FSB using the 333/800 divider and Performance Level 7. Scaling the FSB higher will require further tuning and perhaps returning some of the phases back to AUTO. We must consider that various memory settings can affect the level of TRD adjustments that can be made. Experimentation will be required by the user when changing CPU/RAM MHz (FSB) and also primary/secondary RAM timings.
465FSB BIOS Settings
For our 465 FSB Prime stable test, we used the 333/800 strap. We set Performance Level 7, targeted a 465FSB x 8 CPU speed, and ran 4GB of OCZ Flex 9200. The remaining BIOS DRAM Settings were as follows:
| 465FSB BIOS Settings | |
| CPU Feature | |
| Thermal Management Control | Disabled |
| PPM (EIST) Mode | Disabled |
| Limit CPUID MaxVal | Disabled |
| CIE Function | Disabled |
| Execute Disable Bit | Enabled |
| Virtualization Technology | Enabled |
| Core Multi-Processing | Enabled |
| Exist Setup Shutdown | Mode 2 |
| CLOCK VC0 divider | AUTO |
| CPU Clock Ratio | 8x |
| Target CPU Clock | 3722MHz |
| CPU Clock | 465FSB |
| Boot Up Clock | AUTO |
| DRAM Speed | 333MHz/800MHz |
| Target DRAM Speed | DDR2-1116MHz |
| PCIE Clock | 100MHz |
| Voltage Settings | |
| CPU VID Control | 1.4375 |
| CPU VID Special Add | AUTO |
| DRAM Voltage Control | 2.12 |
| SB 1.05V Voltage | 1.07v |
| SB Core/CPU PLL Voltage | 1.55v |
| NB Core Voltage | 1.65 |
| CPU VTT Voltage | 1.60v |
| VCore Droop Control | Disabled |
| Clockgen Voltage Control | 3.45v |
| GTL+ Buffers Strength | Strong |
| Host Slew Rate | Weak |
| GTL REF Voltage Control | Enabled |
| x CPU GTL1/3 REF Volt | 115 |
| x CPU GTL 0/2 REF Volt | 115 |
| x North Bridge GTL REF Volt | 117 |
| DRAM Timing | |
| Enhance Data transmitting | FAST |
| Enhance Addressing | FAST |
| T2 Dispatch | Disabled |
| Channel 1 CLK Crossing Setting | More Aggressive |
| Channel 2 CLK Crossing Setting | More Aggressive |
| CH1CH2 Common CLK Crossing Setting | More Aggressive |
| CAS Latency Time (tCL) | 5 |
| RAS# to CAS# Delay (tRCD) | 5 |
| RAS# Precharge (tRP) | 4 |
| Precharge Delay (tRAS) | 9 |
| All Precharge to Act | 4 |
| REF to ACT Delay (tRFC) | 30 |
| Performance Level | 7 |
| Read delay phase adjust | SEE BELOW |
| MCH ODT Latency | 1 |
| Write to PRE Delay (tWR) | 12 |
| Rank Write to Read (tWTR) | 10 |
| ACT to ACT Delay (tRRD) | 3 |
| Read to Write Delay (tRDWR) | 8 |
| Ranks Write to Write (tWRWR) | AUTO |
| Ranks Read to Read (tRDRD) | AUTO |
| Ranks Write to Read (tWRRD) | AUTO |
| Read CAS# Precharge (tRTP) | 3 |
| ALL PRE to Refresh | 4 |
| PCIE Slot Config | 1X 1X |
| CPU Spread Spectrum | Disabled |
| PCIE Spread Spectrum | Disabled |
| SATA Spread Spectrum | Disabled |
| TRD Phase adjust settings | |
| Channel 1 Phase 0 Pull-In | ENABLED (TRD 6) |
| Channel 1 Phase 1 Pull-In | ENABLED (TRD 6) |
| Channel 1 Phase 2 Pull-In | ENABLED (TRD 6) |
| Channel 1 Phase 3 Pull-In | ENABLED (TRD 6) |
| Channel 1 Phase 4 Pull-In | ENABLED (TRD 6) |
| Channel 2 Phase 0 Pull-In | ENABLED (TRD 6) |
| Channel 2 Phase 1 Pull-In | AUTO (TRD 7) |
| Channel 2 Phase 2 Pull-In | ENABLED (TRD 6) |
| Channel 2 Phase 3 Pull-In | ENABLED (TRD 6) |
| Channel 2 Phase 4 Pull-In | ENABLED (TRD 6) |
Even though we have set Performance Level 7 in the DRAM page, this particular TRD Phase sequence is virtually running a Performance Level of 6 throughout the entire TRD cycle with the exception of a single TRD phase set to 7 (Channel 2 Phase 1) to create the breathing space necessary for the Northbridge to hold steady at 465FSB with 4GB of RAM. When setting a series of phases to ENABLED on both channels, Channel 2 will require an offset as can be seen in the list of settings we used above. If Channel 1 Phase 0, Phase 1 and Channel 2 Phase 0 are set to ENABLED, Channel 2 Phase 1 must be set to AUTO.
Running two or more corresponding phases at ENABLED on both channels is more aggressive, as it sets the corresponding TRD phase registers to -1 at the same point of the TRD cycle, resulting in a lower latency and thus a higher load on the chipset. The general advantage of TRD phase adjustments is to increase FSB margins while retaining significant amounts of latency and bandwidth at FSBs that fall between the borders of two Performance Levels.
Setting a single channel's phase to ENABLED while the corresponding phase for the other channel is set to AUTO results in a very slight gain in latency and bandwidth, which can be useful for maximizing overall performance.
The above timing and phase combinations are only applicable for the setting of 465FSB using the 333/800 divider and Performance Level 7. Scaling the FSB higher will require further tuning and perhaps returning some of the phases back to AUTO. We must consider that various memory settings can affect the level of TRD adjustments that can be made. Experimentation will be required by the user when changing CPU/RAM MHz (FSB) and also primary/secondary RAM timings.
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Acanthus - Thursday, October 18, 2007 - link
Although all of the tweaking options provided are nice, it literally does no better than Asus P5K Deluxe or the Gigabyte P35-DQ6.Furthermore with X38 boards on the way, im not seeing a whole lot of incentive for this $300 motherboard.
Just my $.02
retrospooty - Thursday, October 18, 2007 - link
This board has hit 672mhz FSB, far FAR higher than any other other board ever, including early samples of X38. Not likely to be matched until the DFI X38 comes out.http://www.xtremesystems.org/forums/showthread.php...">http://www.xtremesystems.org/forums/showthread.php...
This link shows it at 666mhz, I cant find the 672mhz one at the moment, but its on the same forum, by the same guy with the same golden CPU.
cmdrdredd - Thursday, October 18, 2007 - link
Not usable 24/7WHO CARES!?
retrospooty - Thursday, October 18, 2007 - link
Well, it still goes alot higher than the others you mentioned, it is absolutely the best overclocking motherboard available. - that was what I responded too, obviously its not the one for you.Acanthus - Thursday, October 18, 2007 - link
That is from the DFI labs... with a beta board... on supercooling...and volt mods... on a dual core CPU that doesnt stress the PWMs...Anandtechs results even using phase dont approach those results.
retrospooty - Friday, October 19, 2007 - link
No, that is not from DFI labs, that is an independant dood, and CPU's that hit that high FSB are pretty rare.Whatever man, you can poo poo it all you want. It is the best OC mobo out there, and goes higher and takes it farther than any other. It may not be the one for you though.
Raja Gill - Thursday, October 18, 2007 - link
You need to remember that this board was compared at stock settings, not OC'ed, things change up top...;), not to mention we could not get the board to crash..regards
Raja
Acanthus - Thursday, October 18, 2007 - link
Its the same chipset, its not going magically increase in a non-linear fashion.The P5K and DQ6 hit the same maximum overclock.
MadBoris - Thursday, October 18, 2007 - link
It makes sense that article takes a different approach, customers of this board or tweakers in general, will really appreciate the fine details.Personally, in the last ten years I have gotten to a place where I am very comfortable not pushing for the last 100 - 300 mhz. The meager tangible return is not worth all the extra voltage or potential stability issues that often come up later in the life of the HW due to creep, dust, aging paste, etc. I get a nice stress test capable OC, then back it up a notch. I won't win any 3dmark awards that way though but am very satisfied with stability when a new product stresses HW in ways not stressed before.
One thing for sure with this board, I wouldn't want to lose the CMOS, then have to remember all my settings after a year.
Nice board and good article, $300 is too much though for a MB for me. It's definitely elite.
retrospooty - Thursday, October 18, 2007 - link
Its alot of reading, but that is because the DFI is alot of motherboard. I have had it since it was first released and loving every minute of it. I have a C2D 6750 running at 8x500 fsb for a sweet 4 ghz on water at DDR2 1000 4-4-4-10 timing, man is it sweet.There are sooooo many bios tweaks to get better performance, or stability at high overclock - its definitely not for beginners... worth every penny of the $300 I spent.