Performance Level

Leaving this function set to Auto works okay as long as the board is not going to be pushed. One of the issues pertaining to the current BIOS is that the BIOS automatically applies tRD Phase shifts (see the AUTO section below), which prevent the user from running a flat Performance Level unless a value is selected 1 higher than the required value and all the Phase Shift Registers (at least the active ones according to the memory divider) are set to Enabled. So, if you want to run a Performance Level of 7, select 8 and then proceed to set all the tRD Phase shift registers to Enabled, which will in fact give you a tRD of 7.

If the registers are left at AUTO, there's a good chance that the board will fail to POST at higher FSB speeds that happen to fall at the limit of the applied level of tRD. For example if the limit of tRD 6 happens to be at 450 FSB and tRD phase shifts are left to AUTO, some of the channels will pull down to a tRD of 5 resulting in either a non-POST or a system hang during OS loading.


TRD Phase Adjust

This BIOS function is best explored by more advanced tweakers and benchmarkers; our own findings are as follows.

Options for this function are AUTO and ENABLED

Default for all phases is AUTO

AUTO: Unlike the DFI P35 T2R BIOS, setting AUTO will not disable the function of the tRD Phase shift registers; rather the BIOS attempts to apply any phase shifts it thinks are possible. While this works well for the most part, there are times when overclocking that increasing the Performance Level by 1 in the DRAM timing page and setting all the phases to Enabled may be the best course of action.

ENABLED: Sets the corresponding phase of the TRD cycle to -1. If we set a Performance Level of 7 in the DRAM page, using ENABLED for any of the phases will set the Performance Level of the selected Phase to 6, i.e. TRD -1 for the corresponding phase and channel.

Both channels have independent phase adjustments, and the maximum advantage of setting a phase to ENABLED occurs when the same phase from both channels is set to ENABLED simultaneously. Please note not all of the phases are active at all times. The number of active phases is dependent on the memory divider used i.e. the number of FSB cycles that are active in relation to the number of active memory bus cycles.

Toe to Toe with the BIOS (cont'd) Still on our feet (BIOS)
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  • Ephebus - Tuesday, April 29, 2008 - link

    I remember a time when I was considering the purchase of a midrange ASUS motherboard with a reasonable set of overclocking options in the BIOS but no PCI-E clock setting, and there was no information on the specifications page or the manual as to how that setting would behave when overclocking. I then wrote to ASUS asking if the PCI-E clock was always locked by the board at 100 or if it would vary according to the CPU clock setting, and was actually told by an ASUS support "technician" to "go read a book on overclocking". I managed to get the info later on a forum from a person who owned the board and was kind enough to check it out for me. And that is, when ASUS support doesn't simply delete your support inquiry.

    With DFI I've managed to actually have short conversations with the technical support staff in the past, was able to report minor BIOS bugs and see them fixed on the next release, etc., so at least for me it's not just a question of whether a DFI motherboard can reach a few MHz more than an ASUS competitor or not on this or that benchmark, it's also all about the feeling of satisfaction from owning a product made by a company that has this kind of attitude towards users, and that always does their best to meet the needs and wishes of enhusiasts. I'll gladly pay more for a DFI product anytime.
  • Intelman07 - Monday, April 28, 2008 - link

    Is there a reason Anandtech reconmends ~400FSB for quad core, does a lower multiplier and a higher FSB increase performance more in a quad core chip?
  • Rajinder Gill - Monday, April 28, 2008 - link

    Hi Intelman07,

    This applies in relation to the FSB limits of the quad cores only ON THIS board; 400 FSB at a trd running near 5-6 will give you a read delay time of around 13ns. Anything over 420 FSB needs a hike in trd while 440+ you need to be looking twoards a trd of 8 which is a delay of 17ns. The drop in write/copy speed bandwidth by reverting to 400FSB is only 500mbs while reads gain 500mbs running the lower tRD (swings and roundabouts). Now factor the VTT and VMCH requiremnts of the higher FSB and it becomes to click.

    For more insight into this, 2 of our articles here will explain the fundammnetals and reasoning a little better.

    http://www.anandtech.com/mb/showdoc.aspx?i=3208&am...">http://www.anandtech.com/mb/showdoc.aspx?i=3208&am...

    and also logical approach to system tuning using Kris' excellent groundwork.

    http://www.anandtech.com/cpuchipsets/showdoc.aspx?...">http://www.anandtech.com/cpuchipsets/showdoc.aspx?...

    Other boards which vcan hit higher FSB's and low tRDs change these rules a little. But for the most part, the truth is that FSB overcloking on the quads and Joe Public - 400FSB really is realistic and attainable with real stability - and this is important to a majority of our readers. Of course, we still use our cascades from time to time and hammer the boards real hard without any of the logic written here applied.


    The interetsing part comes as no surprise - yup - this all favors unlocked multiplier processors aka QX9650 and 9770 class, just up the FSB - keep the tRD low and hey presto!

    The beauty of this board is that it gets close to that tRD 12.5ns latency time at 400FSB at 1.25VMCH and 8GB of memory with no need for GTL tuning- easy as pie- with performance that you can't swing anywhere else using a 12mb cache quad on this board.

    Hope that clears it up a little..

    regards
    Raja
  • Bozo Galora - Monday, April 28, 2008 - link

    Another great article by AT's best reviewer.

    I have read somewhere DFI's top X48 board gonna have ICH10R and cost ~$400??
  • Slash3 - Monday, April 28, 2008 - link

    Page 2 states "The expansion slot layout is comprised of three PCI Express x16 slots (two x16 and one x4 slot), and three PCI slots."

    The board itself has 3 physical PCI-E 16x slots and 1 PCI-E 4x slot though, so the sentence is kind of ambiguous.
  • takumsawsherman - Monday, April 28, 2008 - link

    It's the wicked fast 400Mbps version, rather than 800Mbps. Wouldn't want to advance the field. Nope, let's use the 10 year old ancient variety, rather than the 5 year old less ancient variety.

    I've got an even better idea... Why not throw in some USB 1.1 ports.
  • Rob94hawk - Monday, April 28, 2008 - link

    I got all excited and then I saw DDR2....

    Might as well just replace PCIE with AGP while their at it.
  • Rajinder Gill - Monday, April 28, 2008 - link

    Just contacted DFI, they are aiming at retail launch of the DDR3 version on the 20th May..

    Review sample boards should ship within the next week..

    regards
    Raja
  • Rajinder Gill - Monday, April 28, 2008 - link

    EDIT: Make that early June for full retail (allowing for shipping time etc)..

    regards
    Raja
  • Rob94hawk - Wednesday, April 30, 2008 - link

    Will be looking forward to it. Thank you.

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